1. Field of the Invention
The present invention relates generally to data communication systems. In particular, the present invention relates to a phase locked loop used in a data communication system which prevents noise contained in an input signal from causing the phase locked loop to be driven out of lock.
2. Description of the Prior Art
In the past, there have been numerous proposals for communications systems which utilize existing power lines to carry the communication signals. One application of this type of communication system is for remote control of appliances and other electrical loads in homes and commercial buildings.
The power line carrier systems normally use a radio frequency (RF) signal which is superimposed with the power line frequency (typically 60 Hz in the United States). The particular data transmission format for the RF signal can take one of several well-known formats.
One advantageous digital data transmission format is frequency shift keyed (FSK) transmission. An FSK transmitter modulates a reference frequency signal based upon the data to be transmitted, so that the transmitted signal has a frequency (f.sub.FSK) which is either slightly greater than or slightly less than the frequency (f.sub.O) of the reference signal. In typical FSK transmission systems, a frequency f.sub.FSK which is greater than f.sub.O represents a digital "1" while a frequency f.sub.FSK which is less than f.sub.O represents a digital "0". An FSK receiver receives and demodulates the transmitted FSK signal to produce a serial data stream at a predetermined data rate (or "baud rate"). Each bit of the data stream is based upon the frequency of the FSK signal during one bit time period.
In the prior art, FSK receivers have often been quite complicated and required expensive high precision components. The cost and complexity of FSK transmission systems has, as a result, limited the applicability of FSK transmitters and receivers in power line carrier communication systems.
One advantageous power line carrier communication system reduces the need for high precision components by synchronizing the FSK signal, the data rate, and all timing signals used by the transmitter and the receiver with the power line carrier frequency. This is achieved by means of a phase locked loop in the transmitter or receiver which locks onto the power line carrier frequency. The phase locked loop includes a voltage controlled oscillator (VCO) which generates an output signal having a frequency at least as high as f.sub.O. The frequency of the VCO output signal is divided to produce all of the timing signals used by the transmitter or receiver, as well as a loop synthesized signal which has the same frequency as the power line frequency when the loop is in lock. A digital tristate phase detector or "sequential" phase detector compares the power line frequency and the synthesized signal, and produces an output signal which is related to the phase difference between the two signals. The phase detector is triggered by rising edges of the two signals. The output of the phase detector is supplied to a loop filter, which produces an oscillator control voltage which determines the frequency of the output of the VCO. The loop seeks a phase locked condition in which the rising edges (e.g. positive zero crossings) of the power line frequency and the loop synthesized signal are synchronous. As a result, the VCO output signal and all of the timing signals derived from the VCO output signal by the timing generation divider circuit are also locked to zero crossings of the power line frequency.
The tristate phase detector used in this communication system is particularly advantageous because it is a simple and easily implemented digital integrated circuit, and because it provides high gain with very small phase errors. On the other hand, the appearance of spurious rising edges (created by noise on the power line) created unwanted digital states which can drive the phase locked loop out of lock. Since the typical power line is prone to various transients and other electrical noise, the adverse effect of noise on the tristate phase detector presents a significant disadvantage to the use of a phase locked loop in this type of a communication system.
One possible solution to the problem of noise is to filter the power line frequency signal before it is applied to the tristate phase detector. This filtering, however, can produce a phase shift which can affect the proper operation of the phase locked loop. In addition, such filters normally require discrete components which increase the cost and thus negate some of the advantages which are otherwise achieved by using a digital tristate phase detector.
Another solution to the noise sensitivity of the phase locked loop is proposed in the previously-mentioned U.S. Pat. No. 4,389,622 to G. Kachman. In this patent application, control circuitry is added to vary the bandwidth of the loop, depending upon whether the phase locked loop is in lock or out of lock. This is achieved by the addition of a lock detector which compares the power line frequency input signal and the loop synthesized signal and produces an output which indicates whether the loop is in lock. The timing generation divider also produces a "window" signal which begins shortly before the anticipated rising edge of the power line frequency input signal and ends slightly after the expected transition. Digital blanking logic controls the application of the power line frequency input signal to the input of the tristate phase detector. When the loop is out of lock, all signal transitions of the input signal are supplied to the input of the phase detector. Once the phase locked loop is in lock, as indicated by the lock detector, the blanking logic edits the power line frequency input signal so that only those transitions which occur during the time period defined by the window signal are applied to the input of the phase detector. Spurious rising edges of the input signal outside of the window are ignored, i.e. they are not permitted to pass to the input of the phase detector. While this system is very effective in reducing the effects of noise on the proper operation of the phase locked loop, there are certain instances in which second order loop error effects are produced due to the editing of the input signal transitions. There is a continuing need, therefore, for an improved system which eliminates the problems of noise in the input to a phase locked loop having a digital tristate phase detector.